VLSI Questions And Answers

1⟩ Explain the difference between write through and write back cache?

Write Through. After writing in cache memory, main memory is

updated too inmediatly to mantain reliability

Write Back After writing in cache memory a flag bit called

dirty bit is set. When this value need to be replaced that

bit is check, if it is set then the value is taken to main

memory

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2⟩ What is the most complicated/valuable program you written in C/C++?

Matrix

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3⟩ If not into production, how far did you follow the design and why did not you see it into production?

Design is a general term,applicable in every field of

engineering.however production is termed as to follow up

the steps after design to make product available in the

market.

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4⟩ What types of high speed CMOS circuits have you designed?

Dynamic CMOS ckts and high speed multipliers using

BOOTh/Mod-Booth algorithm.

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5⟩ What products have you designed which have entered high volume production?

jigs and fixtures

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6⟩ What are the main issues associated with multiprocessor caches and how might you solve them?

issue : Cache coherency or Data coherency. The problem is

all the processors cache should have exactly the same

shared data (cohenrent data). and there are races possible

with multiprocessors.

possible solution: use one central cache controller which

will get all the read/write requests from all the

processors and peripherals so that it can make sure there

are no races and cache coherency is maintained.

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7⟩ Do you know MESI?

Is a widely used cache coherency and memory coherence

protocol introduced by Intel. Modified Exclusive Shared

Invalid are the protocol States.

M means value has been modified from main memory and the

cache is required to write the data back to main memory,

before permitting any other read of the main memory state.

(ITS DIRTY)

E IS CLEAN: Value Match with main memory

S Cache may be stored in other caches of the machine

I Invalid

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8⟩ Suppose For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

the purpose of cache is to reduce the average time to

access the main memory, the operation is like that when the

CPU wants to access the data, it first check the cache, if

an entry can be found with a tag matching that of desired

data, CPU gets the data from cache directly, otherwise, the

data will be copied into cache for next access.

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9⟩ Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine?

1.Instruction fetch

2.decode instruction and read register files

3.execute

4.data to access from memory

5.write back

throughput is the total amount of work done in a given time,

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10⟩ What is the term snooping?

Let's take an example of different processors(along with

their independent caches) sharing the same memory system.

Now if this memory is a Read-Write memory and let's say

that one of the processors writes to this memory after some

data computation, all the processors need to update their

individual cache copies of the now modified memory. To do

this the concept of snooping is implemented. cache snooping

is the means by which each cache constantly

monitors/detects the bus for any write to a memory location

and if a write is found, it invalidates it current copy of

cached memory data and copies the new content over.

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11⟩ Explain How many bit combinations are there in a byte?

1 byte means 8 bits so 256 com

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12⟩ In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

if the input signal is asynchronous with the clock (state

machine clock), then you need to double clock the same

signal to synchronize with the state machine clock.

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13⟩ You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

This is a signal integrity question for board designers.

there are two types of termination schemes viz. series and

parallel termination. series termination is where a resistor

of small value ( rule of thumb 1/2 of characteristic

impedance of the trace ) placed near the source ( near

driver). the parallel termination is a combination of two

resister ( rule of thumb twice the char. impedance f the

trace) placed near the destination ( input) where one

resistor connects the signal trace to the VCC and other

connects to the GNd.

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14⟩ What are the total number of lines written by you in C/C++? What compiler was used?

here we use the lines depends on the programme.But we have

65536 lines which are available in it

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15⟩ What is the difference between = and == in C?

'=' in c is the assignment opperator.whereas '==' is the

logical equality operator.

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16⟩ Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads?

State machine to detect 3 consecutive heads appearing in

multiple tosses;

state 1 : initial state

As long as the toss results in TAIL , in this state

If the toss results in HEAD go to state 2

state 2 : HEAD1 resulted

in the next toss , If TAIL is resulted go to

the initial state1 . If HEAD is resulted go to

state3.

state3 : HEAD2 is resulted

in the next toss , If TAIL is resulted go to

the initial state1 . If HEAD is resulted go to

state4.

state4 : HEAD3 is resulted and this is the final state

As long as the HEAD results in each next toss

be in state 4. If any toss results in TAIL go to

initial state1

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17⟩ What is VHDL and/or Verilog?

vhdl is very high speep integrated chips hardware

descripted language and verilog is to verify logic

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VLSI

Home Computer Embedded Systems VLSI

17 VLSI Questions And Answers

1⟩ Explain the difference between write through and write back cache?

2⟩ What is the most complicated/valuable program you written in C/C++?

3⟩ If not into production, how far did you follow the design and why did not you see it into production?

4⟩ What types of high speed CMOS circuits have you designed?

5⟩ What products have you designed which have entered high volume production?

6⟩ What are the main issues associated with multiprocessor caches and how might you solve them?

7⟩ Do you know MESI?

8⟩ Suppose For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

9⟩ Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine?

10⟩ What is the term snooping?

11⟩ Explain How many bit combinations are there in a byte?

12⟩ In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

13⟩ You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

14⟩ What are the total number of lines written by you in C/C++? What compiler was used?

15⟩ What is the difference between = and == in C?

16⟩ Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads?

17⟩ What is VHDL and/or Verilog?

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VLSI

Home Computer Embedded Systems VLSI

17 VLSI Questions And Answers

1⟩ Explain the difference between write through and write back cache?

2⟩ What is the most complicated/valuable program you written in C/C++?

3⟩ If not into production, how far did you follow the design and why did not you see it into production?

4⟩ What types of high speed CMOS circuits have you designed?

5⟩ What products have you designed which have entered high volume production?

6⟩ What are the main issues associated with multiprocessor caches and how might you solve them?

7⟩ Do you know MESI?

8⟩ Suppose For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

9⟩ Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine?

10⟩ What is the term snooping?

11⟩ Explain How many bit combinations are there in a byte?

12⟩ In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

13⟩ You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

14⟩ What are the total number of lines written by you in C/C++? What compiler was used?

15⟩ What is the difference between = and == in C?

16⟩ Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads?

17⟩ What is VHDL and/or Verilog?

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