⟩ Design a divide-by-3 sequential circuit with 50% duty circle now?
incoming clock by ODD value as assigned in genric
CLK_DIV_BY generic with
50% duty cycle
------------------------------------------------------------
-----------
library IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity FDIV is
generic(
CLK_DIV_BY : INTEGER :=15; --Give the
odd value with which you want to divide the clock i.e.
3,5,7,9
COUNTVALUE : INTEGER :=4 --Give the bit
count of division ratio value.Ex upto 3= 2 bits; 5 to 7 =
3; 9 to 15 = 4 and so on..
);
port(
CLK : in std_logic;
CLR : in std_logic;
DIV: out std_logic
);
end FDIV;
--------------------------------------------------
Architecture beh of FDIV is
signal DIV_pos, DIV_neg :std_logic;
signal posedgecounter :std_logic_vector((COUNTVALUE - 1)
downto 0);
signal negedgecounter,test :std_logic_vector((COUNTVALUE -
1) downto 0);
begin
-----------------------------
PROCESS(CLK,CLR)
begin
IF ( CLR = '0') THEN
posedgecounter <= (others =>'0');
ELSIF RISING_EDGE(CLK) THEN
posedgecounter <= posedgecounter + 1;
if posedgecounter = conv_std_logic_vector((CLK_DIV_BY -
1),(COUNTVALUE)) then
posedgecounter <= (others =>'0');
end if;
if posedgecounter <= conv_std_logic_vector(((CLK_DIV_BY -
1)/2),(COUNTVALUE)) then
DIV_pos <= '1';
else
DIV_pos <= '0';
end if;
END IF;
END PROCESS;
------------------------------
PROCESS(CLK,CLR)
begin
IF ( CLR = '0') THEN
negedgecounter <= (others =>'0');
ELSIF FALLING_EDGE(CLK) THEN
negedgecounter <= negedgecounter + 1;
if negedgecounter = conv_std_logic_vector((CLK_DIV_BY -
1),(COUNTVALUE)) then
negedgecounter <= (others =>'0');
end if;
if negedgecounter <= conv_std_logic_vector
(((CLK_DIV_BY -1)/2),(COUNTVALUE)) then
DIV_neg <= '1';
else
DIV_neg <= '0';
end if;
END IF;
END PROCESS;
----------------------------------------
DIV<= DIV_pos and DIV_neg;
----------------------------------------
end beh;
