The Transmission-Gate input is connected to the D_LATCH
data input (D), the control input to the Transmission-Gate
is connected to the D_LATCH enable input (EN) and the
Transmission-Gate output is the D_LATCH output (Q)
What are the main issues associated with multiprocessor caches and how might you solve them?
Do you know MESI?
Suppose For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine?
What is the term snooping?
Explain How many bit combinations are there in a byte?
In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
What are the total number of lines written by you in C/C++? What compiler was used?
What is the difference between = and == in C?
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