⟩ Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflowing or overflowing?
Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflowing or overflowing?
RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%
Assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for 1000ns, due to (3), so 3000ns of the enable we are doing no output work.
Therefore, FIFO size = 3000ns/40ns = 75 entries.
