Electrical Engineering

  Home  Engineering  Electrical Engineering


“Electrical engineering interview questions and answers, referred to as electrical and electronic engineering, Electrical Engineering interview questions and answers guide deals with the study and application of electricity, electronics and electromagnetism. The field interview questions and answers first became an identifiable occupation in the late nineteenth century after commercialization of electric telegraph and electrical power supply. Learn Electrical Engineering by interview questions”



105 Electrical Engineering Questions And Answers

1⟩ Given the following Verilog code, what value of "a" is displayed?

Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

a = 0;

a <= 1;

$display(a);

end

This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

1: Active Events (blocking statements)

2: Inactive Events (#0 delays, etc)

3: Non-Blocking Assign Updates (non-blocking statements)

4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue.

Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

 207 views

3⟩ What is the difference between a Verilog task and a Verilog function?

The following rules distinguish tasks from functions:

A function shall execute in one simulation time unit;

a task can contain time-controlling statements.

A function cannot enable a task;

a task can enable other tasks or functions.

A function shall have at least one input type argument and shall not have an output or inout type argument;

a task can have zero or more arguments of any type.

A function shall return a single value; a task shall not return a value.

 219 views

4⟩ What is the difference between the following two lines of Verilog code?

What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;

#5 a = b; Wait five time units before doing the action for "a = b;".

The value assigned to a will be the value of b 5 time units hence.

a = #5 b; The value of b is calculated and stored in an internal temp register.

After five time units, assign this stored value to a.

 195 views

5⟩ Using the given, draw the waveforms for the following versions of a?

Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not in the same run):

reg clk;

reg a;

always #10 clk = ~clk;

(1) always @(clk) a = #5 clk;

(2) always @(clk) a = #10 clk;

(3) always @(clk) a = #15 clk;

Now, change a to wire, and draw for:

(4) assign #5 a = clk;

(5) assign #10 a = clk;

(6) assign #15 a = clk;

 223 views

6⟩ Given the following snipet of Verilog code draw out the waveforms for clk?

Given the following snipet of Verilog code, draw out the waveforms for clk and a

always @(clk) begin

a = 0;

#5 a = 1;

end

10 30 50 70 90 110 130

___ ___ ___ ___ ___ ___ ___

clk ___| |___| |___| |___| |___| |___| |___| |___

a ___________________________________________________________

This obviously is not what we wanted, so to get closer, you could use

"always @ (posedge clk)" instead, and you'd get

10 30 50 70 90 110 130

___ ___ ___ ___ ___ ___ ___

clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___

a _______________________| |___________________| |_______

 200 views

7⟩ Explain the differences between "Direct Mapped", "Fully Associative", and "Set Associative" caches

If each block has only one place it can appear in the cache, the cache is said to be direct mapped. The mapping is usually (block-frame address) modulo (number of blocks in cache).

If a block can be placed anywhere in the cache, the cache is said to be fully associative.

If a block can be placed in a restricted set of places in the cache, the cache is said to be set associative. A set is a group of two or more blocks in the cache. A block is first mapped onto a set, and then the block can be placed anywhere within the set. The set is usually chosen by bit selection; that is, (block-frame address) modulo (number of sets in cache). If there are n blocks in a set, the cache placement is called n-way set associative.

 229 views

8⟩ Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflowing or overflowing?

Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflowing or overflowing?

RULES:

1) frequency(clk_A) = frequency(clk_B) / 4

2) period(en_B) = period(clk_A) * 100

3) duty_cycle(en_B) = 25%

Assume clk_B = 100MHz (10ns)

From (1), clk_A = 25MHz (40ns)

From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for 1000ns, due to (3), so 3000ns of the enable we are doing no output work.

Therefore, FIFO size = 3000ns/40ns = 75 entries.

 214 views

9⟩ Write a function to determine whether a string is a palindrome (same forward as reverse, such as "radar" or "mom")

/* BEGIN C SNIPET */

#include

void is_palindrome ( char *in_str ) {

char *tmp_str;

int i, length;

length = strlen ( *in_str );

for ( i = 0; i < length; i++ ) {

*tmp_str[length-i-1] = *in_str[i];

}

if ( 0 == strcmp ( *tmp_str, *in_str ) ) printf ("String is a palindrome");

else printf ("String is not a palindrome");

}

/* END C SNIPET */

 197 views

11⟩ Draw the state diagram for a circuit that outputs?

Draw the state diagram for a circuit that outputs a "1" if the aggregate serial binary input is divisible by 5. For instance, if the input stream is 1, 0, 1, we output a "1" (since 101 is 5). If we then get a "0", the aggregate total is 10, so we output another "1" (and so on).

We don't need to keep track of the entire string of numbers - if something is divisible by 5, it doesn't matter if it's 250 or 0, so we can just reset to 0. So we really only need to keep track of "0" through "4".

 199 views

12⟩ Write a function to output a diamond shape according to the given (odd) input?

Examples: Input is 5 Input is 7

* *

*** ***

***** *****

*** *******

* *****

***

*

### BEGIN PERL SNIPET ###

for ($i = 1; $i <= (($input * 2) - 1); $i += 2) {

if ($i <= $input) {

$stars = $i;

$spaces = ($input - $stars) / 2;

while ($spaces--) { print " "; }

while ($stars--) { print "*"; }

} else {

$spaces = ($i - $input) / 2;

$stars = $input - ($spaces * 2);

while ($spaces--) { print " "; }

while ($stars--) { print "*"; }

}

print "n";

}

### END PERL SNIPET ###

 188 views

14⟩ In C, explain the difference between the & operator and the * operator?

& is the address operator, and it creates pointer values.

* is the indirection operator, and it preferences pointers to access the object pointed to.

Example:

In the following example, the pointer ip is assigned the address of variable i (&i). After that assignment, the expression *ip refers to the same object denoted by i:

int i, j, *ip;

ip = &i;

i = 22;

j = *ip; /* j now has the value 22 */

*ip = 17; /* i now has the value 17 */

 190 views

15⟩ Write the code to sort an array of integers?

/* BEGIN C SNIPET */

void bubblesort (int x[], int lim) {

int i, j, temp;

for (i = 0; i < lim; i++) {

for (j = 0; j < lim-1-i; j++) {

if (x[j] > x[j+1]) {

temp = x[j];

x[j] = x[j+1];

x[j+1] = temp;

} /* end if */

} /* end for j */

} /* end for i */

} /* end bubblesort */

/* END C SNIPET */

Some optimizations that can be made are that a single-element array does not need to be sorted; therefore, the "for i" loop only needs to go from 0 to lim-1. Next, if at some point during the iterations, we go through the entire array WITHOUT performing a swap, the complete array has been sorted, and we do not need to continue. We can watch for this by adding a variable to keep track of whether we have performed a swap on this iteration.

 178 views