"IRQ is serviced at a normal priority level and FIQ is

serviced at high priority level." This statement is wrong

FIQ is the fast interrupt i.e. the latency time taken is less because in the FIQ mode (in case of ARM architecture where these modes are encountered) the mode has an additional set of 8 general purpose registers which means in case of the banked registers there is no need to store these registers into stack when the interrupt occurs.

That means r0 to r7 only needs to be stored while moving from User mode to FIQ mode whereas while moving from to IRQ mode r0 to r12 needs to be stored.