86 Family

Put even number of not gates between clocks of reg A and

Reg B. The not gates will introduce delay between clock of

reg A and reg B.

The Transmission-Gate input is connected to the D_LATCH

data input (D), the control input to the Transmission-Gate

is connected to the D_LATCH enable input (EN) and the

Transmission-Gate output is the D_LATCH output (Q)

put one bubble in front of xor gate....