1⟩ Explain The CPU is busy but you want to stop and do some other task. How do you do it?
Arise a non maskable interrupt.
Then give jump instruction to required subroutine.
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Arise a non maskable interrupt.
Then give jump instruction to required subroutine.
The latency of the architecture increases with the pipeline stages. Penalty due to the flushing of the pipeline for instance will also increase Cycles Per Instruction of the CPU architecture
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining. There are three classes of Hazards:
1. Structural Hazards: It arise from resource conflicts when the hardware cannot support all possible combinations of instructions simultaniously in ovelapped execution.
2. Data Hazards: It arise when an instruction depends on the results of previous instruction in a way that is exposed by the ovelapping of instructions in the pipeline.
3. Control Hazards: It arise from the pipelining of branches and other instructions that change the PC.
computer have different type of memory like primary memory , Auxiliary memory , buffer memory , Cache memory , virtual memory ,
the work of all memory heterogeneously primary memory is directly communicate with the CPU . Auxiliary memory are used for storing the data for long time . Buffer memory are mainly used for storing the intermediate data between the travel . cache memory are used for storing the those data that currently required at process time for increase the speed of the data . virtual memory are put in between the two memory for increase the speed of data or instruction it means it put between HDD and RAM .
Virtual memeory is that when the available RAM memory is not sufficient for the system to run the current applications it will take some memory from hard disk.This memory is termed as Virtual memory
Vertical microcode can be considered to be a segment of code or operators that have been clubbed together into fields. In this field every micro operation is given a unique value.
★ A no operation NOP can be included in each field if necessary.
★ The remaining micro operations can be distributed among the other operation field bits.
★ Also micro operations that modify the same registers could be grouped together in the same field.
An instruction can be considered to be a command that has been issued to a computer to perform a particular operation. The instruction format contains various field in them such as:
★ Operation Code Field:
Also known as the op code field, this field is used to specify the operation to be performed for the instruction.
★ Address Field:
This field as its name specifies is used to designate the various addresses such as register address and memory address.
★ Mode field:
This field specifies as to how effective address is derives or how an operand is to perform.
★ For ex. ADD R0, R1. In this case the ADD is the operand whereas the R1, ans R0 are the address fields.
Considered to be the simplest this method involves the updating of the main memory corresponding to every write operation. With this the cache memory is also updated in parallel in case it also contains the word specified at the address. The primary advantage of this method is data integrity, the primary and the cache memory both contain the same data.
The micro-operations in computers are classified into the following categories:
★ Register transfer micro-operations:
These type of micro operations are used to transfer from one register to another binary information.
★ Arithmetic micro-operations:
These micro-operations are used to perform on numeric data stored in the registers some arithmetic operations.
★ Logic micro-operations:
These micro operations are used to perform bit style operations / manipulations on non numeric data.
★ Shift micro operations:
As their name suggests they are used to perform shift operations in data store in registers.
In this method only the location in the cache is updated. Whenever such an update occurs a flag is set which makes sure that in case the word is removed from the cache the correct copy is saved to the main memory. This approach is usually taken when a word is constantly updated at frequent intervals.
These types if interrupts can occur only during the execution of an instruction. They can be used by a programmer to cause interrupts if need be. The primary purpose of such interrupts is to switch from user mode to supervisor mode.
They are also known as traps and their causes could be due to some illegal operation or the erroneous use of data. Instead of being triggered by an external event they are usually triggered due to any exception that has been caused by the program itself. Some of the causes of these types of interrupts can be due to attempting a division by zero or an invalid opcode etc.
These types of interrupts generally come from external input / output devices which are connected externally to the processor. They are generally independent and oblivious of any programming that is currently running on the processor.
The instruction sets can be differentiated by
* Operand storage in the CPU
* Number of explicit operands per instruction
* Operand location
* Operations
* Type and size of operands
Snooping is the process where the individual caches monitor address lines for accesses to memory locations that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location.
Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory
1. Convert to Decimal: (Ax16pow3)+(Cx16pow2)+(Bx16pow1)+(Fx16pow0)
2. Do not try to compute the whole result as any ways we have to divide the number by 16 which results in
(Ax16pow2)+(Cx16pow1)+(Bx16pow0)+(Fx16pow-1)
3. Now get the result as 2928.93 in decimal.
The MESI protocol is also known as Illinois protocol due to its development at the University of Illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory coherence protocol.
MESI is the most common protocol which supports write-back cache. Its use in personal computers became widespread with the introduction of Intel's Pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"
Please share your answer we have still looking for answer or this question
1)address lines to refer to the address of a block
2)data lines for data transfer
3)IC chips 4 processing data